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In ARM, the SPSR is a banked register i.e. after every change in mode, CPSR is copied into the SPSR, and after the mode returns, the SPSR is copied back to CPSR. Why is the CPSR not banked directly? It seems like there are two additional instructions with every mode change (copy into spsr, copy into cpsr)

WrinkleFree
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    not really instructions, copying the data back and forth, the architecture if you could look at it may not have any cost at all, banking would be a cost of more flip flops. Arms are not microcoded so this copy takes no time, one of the clock cycles dealing with the interrupt/event can also in parallel save the cpsr. Likewise on the return. Basically a bank switch and a copy of the cpsr take the same exact amount of time. One clock edge with a little setup time. – old_timer Sep 05 '13 at 15:14

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Manual mode changes are not an efficiency goal on the ARM. Typically, manual mode changes are only done to setup stacks, etc at boot or initialization time.

The cpsr is the active copy. Why do we have a banked lr register but not the current pc? The spsr is a banked cpsr for a different mode; just like the banked lr is the pc for a different mode. The banking is so that the exception state can be transparent. The spsr is banked as an interrupt or data abort may occur in any mode; we need to save it so that we stack execution correctly. The normal unbanked user mode never stacks with another mode. mode changes are done automatically in exception conditions.

The mode registers are setup to make exception handling very efficient and flexible. Manual mode changes are not highly convenient as they are not normally used. You can copy any banked register to an un-banked one before switching modes so that the state can be transferred between the two; this is common when system mode is used for all exception handling. In this case, the registers are often stored to a task context block by the kernel and this is not an efficiency issue as there are memory stores that will pipeline.

artless noise
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  • In the *system mode* case, the *exception* `sp` may be used as a general purpose register. The destination *system mode* contains a real *stack* which often includes a *task control block* via a mask. The last part is common to many OS designs, not specific to the **ARM**. – artless noise Sep 05 '13 at 17:25