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I am new to ARM and bit confused on the concept of Bank registers.Arm related docs say that Each mode has its own set of banked register except user mode .My confusion is that Do every mode has register from r0-r15+banked register.If so. then FIQ mode has highest number of register available to it which is 23 total registers .

Also,it is said about ARM register out of total 37 register ,20 are register are hidden from program at different times.what does it mean??

Amit Singh Tomar
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  • possible duplicate of [What does 'bank'ing a register mean?](http://stackoverflow.com/questions/13432297/what-does-banking-a-register-mean) – artless noise Nov 01 '13 at 14:23
  • A [Helpful list on this topic](http://stackoverflow.com/search?q=[arm]+banked+is%3Aquestion+closed%3Ano). – artless noise Nov 01 '13 at 14:24
  • [Why is CPSR not banked](http://stackoverflow.com/questions/18638711/why-is-cpsr-not-a-banked-register) gives some more insight into `lr` and `cpsr` in regards to banking. – artless noise Nov 01 '13 at 16:56

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I always find this figure informative:

Organization of general-purpose registers and Program Status Registers

Organization of general-purpose registers and Program Status Registers

auselen
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  • Thanks @auselen .Would you confirm this statement that every mode has register from r0-r15+banked register and FIQ Mode has highest number of register visible to it. – Amit Singh Tomar Nov 01 '13 at 10:54
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    Maybe helpful, [Linux FIQ](http://stackoverflow.com/questions/18690715/accessing-kernel-driver-data-from-fiq-interrupt-handler-failing), [Linux multi-FIQ](http://stackoverflow.com/questions/14936928/registering-multiple-fast-interrupt-sources-on-arm-linux), [Linux FIQ register source](https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/kernel/fiqasm.S). The *Linux FIQ register source* use a memory location to load all banked FIQ registers, for example. All registers (banked/non-banked) exist in every mode (they are saved/not wiped out); only r0-r15 can be accessed. – artless noise Nov 01 '13 at 15:33
  • @artless noise ,I was asked in interview that which mode has highest number of register in ARM and interviewer himself told FIQ mode has 23 registers available to it ,FIQ mode has to maintain this list of register all rthe time and when returning from interrupt it will restore banked register to normal register. – Amit Singh Tomar Nov 01 '13 at 16:13
  • @AmitSinghTomar That is wrong. All banked registers are *saved*. You can only access the *FIQ* version of r8-r12 in *FIQ* mode. You have to switch modes to get the other versions. It is the same with the mode stack pointers. Normally, the mode `lr` is set by an exception. As opposed to *banked*, the exception `lr` is conceptually like an alternate meaning. To a hardware person, they would just call it *banked*; the user `lr` state is retained when you return to user mode. – artless noise Nov 01 '13 at 16:45
  • there are 7 separate stack pointer registers for example. But as a programmer you can only use one at a time, base on the mode you are in. There are 30 some general purpose registers, but you can only access 16 at a time. The diagram above which you should have read when you found out about all of this, completely describes the answer. What based on what mode you are in you have access to one column of registers r0-r15, some are user/system mode, and sometimes others are used instead. – old_timer Nov 01 '13 at 20:36