How to access a 40-bit address bus with two 16-bit registers only?

Question

This was a question that was asked in one of my exams which means it's possible.
The question was if I have a 40-bit address bus, how can I access all of its memory locations using two 16-bit registers only. The traditional shifted-addition-method would work up to a 32-bit address bus only, so I was wondering what the answer is or what the method would be.

Answer 1

If we could store each of the possible 40-bit numbers in only 32-bits that would be a logic defying feat, and the inventor of such would win awards!

Naïvely, if all one has is 32 bits, there's no way to differentiate between 2^40 different values.

It seems like a trick question though.

So, what could be done, is to use a word-size of 256 bytes, then the 32-bits only need differentiate between each possible 256-byte word, which only takes 32 bits.  In some sense, the 32 bits would apply to the upper 32 bits of the 40 bit address space, and the remaining lower 8 bits would always be zero.  In such a scheme, all memory locations would be accessible — just need a huge word size!

Answer 2

A 32-bit value only has 2^32 possible values, but a 40-bit address space has 2^40 bytes. You need some extra bits to come from somewhere, e.g. set up ahead of time in something like a segment base, or loaded from memory on every use.

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You could have it work like 286 or 386 protected mode, where one of those 16-bit registers indexes a table in memory (GDT or LDT) that has larger segment-base addresses. In actual 386, the max segment base is near the top of 32-bit address-space, but if you really want to grow the address-space without widening registers to more than a tiny fraction of it at once, you could have the segment-base be 40 bits.

Or like 6502 where there's a memory-indirect addressing mode that loads a wider pointer from memory and uses it. In 6502's case, the zero page, the low 256 bytes of memory, are usable for this, allowing access to 65536 bytes of memory with one 8-bit register or immediate, plus a 16-bit pointer that only has to live in memory. See the X, Indirect addressing mode.

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Without depending on a wider pointer in memory, you could have a special instruction to copy an aligned block of high memory down to a range where it could be addressed normally with byte granularity.

e.g. copy_from_high256 dst, src1:src2 could use src1:src2 as a 32-bit value to be left shifted by 8 bits, making a 40-bit linear address that's aligned by 256. dst could whatever normal way of specifying an address, or an implicit destination like 0. You'd have a corresponding instruction to copy the other way. You might have these instructions take a count, or expect them to be run in a loop.

So you can grab any 256-byte chunk of aligned data you want, letting software manually "page" data to/from high memory as a backing store, into their normally accessible address space that's byte addressable with some other style of addressing mode.

This couldn't be the machine's normal addressing mode for all instructions, unless the word size is 256 bytes (2048 bits)!