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For example, in an 4-core system with 2-way SMT, you have 8 harts, which is it? 4 separate x0-x31 registers ,pc, and csrs, or 8 separate x0-x31, pc, and csrs?

Peter Cordes
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May
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    Each hart has its own execution context, which includes register state. That's how it can look like a separate core for a thread running on it. Those architectural registers might both be renamed onto the same physical register file, but the allocator (RAT) would have to ensure they didn't step on each other. e.g. see Paul Clayton's comment on [Is duplication of state resources considered optimal for hyper-threading?](https://stackoverflow.com/posts/comments/59176118) – Peter Cordes May 06 '22 at 04:43
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    If there were only four copies of `x0`, where would the other four `x0` values be kept when they weren't executing? (And if you decide that they are kept in some secret location, then that secret location is the other four copies of `x0`!) – Raymond Chen May 06 '22 at 04:46
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    Near duplicate of [Hyper Threads, SIPI and Registers](https://stackoverflow.com/q/39075942) – Peter Cordes May 06 '22 at 04:48
  • thanks for the answer,so logically i can assume there're 8 of them, but physically there're 4. – May May 06 '22 at 04:56
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    No, as Raymond said, there has to be enough register-file storage for 2 copies of the registers on each physical core. That might be as part of a physical register file that's more than twice as large, though. e.g. https://www.realworldtech.com/haswell-cpu/3/ for an x86 CPU with 2-way SMT. See also https://www.lighterra.com/papers/modernmicroprocessors/ – Peter Cordes May 06 '22 at 05:19
  • does that mean logically there are 8 of them, but actually it's allocating and renaming them from physical register resource pool? – May May 06 '22 at 05:29
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    Each physical core is of course separate, but within one physical core, yes the two sets of x0..31 state could be renamed onto a larger physical register file on a RISC-V with out-of-order exec. Or an in-order design could just replicate a register file for each hart. (The PC is normally handled specially in a pipelined core, even in-order, and CSRs might just be replicated, not renamed, since they change infrequently.) – Peter Cordes May 06 '22 at 05:47

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