1

I read the introduction of the CR0.CD flag in both the AMD and Intel manuals and get the following 2 questions:

  1. Does the setting of CR0 affect all cores? In other words, does each core have a separate set of control registers?
  2. Does setting the CD flag to 1 only disable the internal caches, or the external caches also disabled as well? The interpretation of Intel and AMD are different.
Peter Cordes
  • 328,167
  • 45
  • 605
  • 847
ShelterRin
  • 183
  • 5
  • 2
    You are really asking two different questions here. As for (1), each core has its own set of registers and does not affect the others. As for (2), I don't know. – fuz Mar 04 '22 at 17:08
  • 1
    @fuz: minor caveat: `CR0.CD` is per *physical* core; logical cores sharing the same physical core *are* all affected when one of them executes a `mov cr0, rax`. [How to explicitly load a structure into L1d cache? Weird results with INVD with CR0.CD = 1 on isolated core with/without hyperthreading](https://stackoverflow.com/q/66772632) shows the consequences of that for messing around with `invd` and no-fill mode. But yes, otherwise control registers are per-logical-core, and definitely not shared across physical cores. – Peter Cordes Mar 05 '22 at 01:52

0 Answers0