The practice problem would be improved by stating complete CPU instructions up front. The processor only runs complete instructions: it never has to run an addressing mode without the context of a complete instruction, which will include an opcode and operand specifiers.
Without the complete instruction, operand sizes are not specified (though here generally appear intended as 32 bit), and an lea opcode, where possible, instead of mov would produce vastly different results. The processor can use addressing modes as targets as well as for sources, but targets write to memory rather than reading from memory — yet as far as we are told we don't know whether the addressing mode is for read or write.
So, there is plenty of room for improvement in the practice problem, by not abstracting a complete instruction down to one addressing mode operand (or else by making other things we will have to assume more explicit).
With the exception of the first (because %rax is 64 bits) imagine that each of these other addressing modes appears as if in a mov instruction as follows:
For example, given 260(%rcx,%rdx) imagine it as this: mov 260(%rcx,%rdx), %edi — and that the question is, what value appears in %edi after each such mov instruction.
The values of certain registers are given, as are the values of the certain memory locations. So, what you need to do is be the computer running each such mov instruction, and reporting what value appears in %edi after.
So, mov 260(%rcx,%rdx), %edi says take 26010 which is also 10416 aka 0x104 and add that to the value held in %rcx, which is given as 1, and also to the value held in %rdx, which is given as 3, to form the effective address, here then, 0x104+1+3 = 0x108. Now use that effective address to load a 32 bit value from that memory location, address 0x108, whose value is given as 0x13.
With a complete instruction, as I've shown, you should be able to consult an instruction set manual to see how it will execute, and derive answers given that execution and the given values in the practice problem table.