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I am working in Vivado using Verilog. Assume I have 2 registers:

reg [3327:0]a;
reg [1023:0] b;

Each clock cycle Id like to take the 13 bits from a and 4 bits from b and multiply them.

Clock 1: a[12:0] * b[3:0]

Clock 3: a[25:13] * b[7:4]

What is the most efficient way to iterate through these registers? Something tells me that using a for loop like this would not be correct?

Daftyler
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  • I suppose I mean proper/least amount of resources? When I use a for loop it seems to want a constant in the reg[constant]. So using like reg[counter: counter-4] throws errors. – Daftyler Jul 05 '21 at 19:35
  • Ah, yes I had read about this and was unable to get the syntax correct, that link was useful! I think I understand now how it should be done. Thank you for your efforts. – Daftyler Jul 05 '21 at 19:56

1 Answers1

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As noted by @toolic, Iterating using a loop is a fine way to do it and using the syntax found here

Daftyler
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