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I have recently read about SPARC. The wiki page that it is a register-register type architecture. The page on x86 says that it is a register-memory type a. Could someone explain the difference between the two types perhaps with a hypothetical example.

Peter Cordes
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randomusr
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2 Answers2

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Register-register is a synonym of load-store.

Directly from Wikipedia:

In computer engineering, a register–memory architecture is an instruction set architecture that allows operations to be performed on (or from) memory, as well as registers.

In a register–memory approach one of the operands for ADD operation may be in memory, while the other is in a register.

This differs from a load/store architecture (used by RISC designs such as MIPS) in which both operands for an ADD operation must be in registers before the ADD.

Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures.

Enrico Migliore
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    Some? Isn't it a defining characteristic of RISC? – user253751 Mar 31 '21 at 22:28
  • That "Some" comes directly from Wikipedia. – Enrico Migliore Apr 01 '21 at 06:13
  • @user253751: I'm not aware of any RISCs that aren't load-store machines. If a machine allowed `add reg, reg, [memsrc]`, I'd be highly reluctant to call it a RISC, even if it had fixed-width instructions and various other RISC features. There are some load-store machines that aren't fully RISCy, like ARM blurs the lines a bit with its load-multiple and store-multiple (which can be used for pop and push with the stack-register), and especially its predicated execution in 32-bit mode. (AArch64 still has lots of complexity, but only in ways that are easy to pipeline, like immediate encoding.) – Peter Cordes May 19 '22 at 04:52
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x86 is a CISC that allows register-memory like add eax, [rdi], but also register-register like add edx, ecx. (And even memory-register, with an RMW memory destination like add [rdi], ebx.)

That kind of CISC doesn't slot nicely into this taxonomy. (https://www.realworldtech.com/architecture-basics/2/ has some more about those styles of machines). This taxonomy is really too simplistic because it doesn't capture the difference between machines that have multiple registers and don't have to use memory all the time, vs. earlier simple machines where most code really did use most instructions with one memory operand (and the other being a register). e.g. some 8-bit micros like 6502 had an OR instruction that could only have a memory source (https://www.masswerk.at/6502/6502_instruction_set.html), vs. others like 8080 that could have a memory source, or one of its other registers. (But still only into the accumulator, hence the ora mnemonic, e.g. ora b does a |= b, vs. x86 making both operands your choice of register for most simple instructions.)

Do note that x86 can't do memory-memory (e.g. add [rdi], [rsi] is not encodeable, unlike VAX where both operands can independently be register or memory with a complex addressing mode). Why isn't movl from memory to memory allowed? explains the CPU-architecture / machine-code reasons why not.

See also What kind of address instruction does the x86 cpu have? - x86 is a 2-operand CISC machine for most normal legacy instructions, but 3-operand for AVX SIMD instructions, and for some scalar integer... It's not the most regular ISA ever :P

A related way to classify machines is that SPARC (like all(?) RISCs) is a load-store machine: the only instructions that can access memory are load and store. You can't have a memory operand to a normal ALU instruction like add.

"load-store" machine is synonymous with register-register, but not being a load-store ISA doesn't imply any specific format.

Peter Cordes
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