Is assigning an unsigned size, contingous memory struct an atomic operation?

Question

I'm supposed to write multiple fields in a register. The vendor "API" is a struct mapped to a memory address. The struct looks something like this:

typedef struct
{
    unsigned Reg_A : 28;
    unsigned Reg_B : 1;
    unsigned Reg_C : 3;
}RegisterFooFields;

typedef union
{
    unsigned U;
    RegisterFooFields B;
}RegisterFoo;

I'm supposed to write all of A, B, and C atomically, as one constrains the other. Does C guarantee that to happen if I assign to RegisterFoo.B?

RegsiterFooFields fields = {.A = 123, .B = 0, .C = 0b10};
RegisterFooAddress->B = fields; /* Is this an atomic write (mov) operation? */

My environment is C99, 32-bit.

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EDIT:

RegisterFooAddress is declared volatile.

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EDIT 2:

What I'm afraid for is the compiler generating a series of assignments for each field, masked appropriately, resulting in a transient register state where (e.g.) Reg_A has been updated but Reg_B and Reg_C have not, leading to the hardware possibly reading the transient state.

Reading the generated assembly is not feasible in case of aggressive optimization, possibly inlining the code.

Answer 1

Does C guarantee that to happen if I assign to RegisterFoo.B?

No, it does not. There is no such guarantee.

But it may be possible that on your platform your compiler compiles it to one single instruction, making it "atomic". Check your compiler documentation, check the generated assembly.

To be sure, I would write a code with volatile access. I usually expect volatile accesses to be "atomic" in the sense that they are compiled to a single mov instruction if the architecture supports it, like:

void RegisterFoo_assign_RegisterFooFields(RegisterFoo *reg, RegisterFooFields fields) {
      static_assert(sizeof(RegisterFooFields) == 4, "");
      static_assert(sizeof(RegisterFoo) == 4, "");
      static_assert(sizeof(unsigned) == 4, "");
      static_assert(_Alignof(unsigned) == _Alignof(RegisterFoo), "");
      unsigned var;
      memcpy(&var, &fields, 4);
      *(volatile unsigned*)reg = var;
      // or really just:
      *(volatile unsigned*)&reg->U = var;
}

The generated assembly from gcc looks nice on godbolt.

Answer 2

If we consider hardware registers mapped into the address space and hardware specification does not guarantee the strong ordering of the accesses there is no mechanisms in the C language to guarantee coherency even if the processor uses instruction which is atomic.

So the atomicity does not guarantee that the return value of this function will be the same as its parameter

volatile uint32_t *reg = (void *)0xE0000454; // some address of the hardware register

uint32_t writeAndRead(uint32_t val)
{
    *reg = val;
    return *reg;
}

In this case, some barriers have to be used. Sometimes it is enough to use Core instructions, sometimes more complex solutions are necessary.

static inline __attribute__((always_inline)) void __DSB(void)
{
  asm volatile ("dsb 0xF":::"memory");
}

uint32_t writeAndRead1(uint32_t val)
{
    *reg = val;
    __DSB();
    return *reg;
}