2

I'm doing some experiments with a ARM Cortex A-8 device running Linux kernel.

I can access and read the value of the L2 cache lockdown register without any problems:

asm volatile ("mrc p15, 1, %0, c9, c0, 0" : "=r" (i));

When I try to write the value back, the device immediately crashes:

asm volatile ("mcr p15, 1, %0, c9, c0, 0" : : "r" (i));

The code is running as a kernel module so there are no permission issues.

I wonder if I'm missing anything special before writing that register value?

Cinar
  • 183
  • 1
  • 1
  • 11

1 Answers1

3

There's a long checklist you need to be careful about if you're going to play with cache lockdown. ARM's information center has a few tips: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344i/Chdeghcb.html

In particular, ensure you have interrupts disabled, and appropriate instructions/data invalidated. Also check that read/write access is enabled - which it might not be even if you're in kernel mode. You need to ensure your code isn't crossing pages or cache lines at critical points. It's really tricky to get right. You can't just set a cache-way locked and expect everything to be work, and you can't just do it with inline ASM in C.

Worst case you'll end up jamming the internal state machine of the L2 cache controller, locking the wrong data down, preventing data from caching altogether and causing everything to abort, or getting the tags out of sync. That'll explain the crash.

Also, is this just experimentation or are you trying to boost performance? It's useful for avoiding touching DRAM/bus for well crafted code sequences, for example if you want to turn it off (deep sleep), but it's not usually a performance win.

John Ripley
  • 4,434
  • 1
  • 21
  • 17
  • Also, find out the revision of the core in your device. Check ARM's website for errata on that rev of Cortex A-8. There's a surprisingly large errata, mostly non-user visible, but hey you're playing with the system :) – John Ripley Mar 01 '11 at 07:53