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I want to know about List Register in GIC v2.

I'm reading ARM Generic Interrupt Controller specification.

This explain all of the registers that are used for interrupt control and for virtualization.

And also if it's a banked register, they say it as a banked register like bellow.

enter image description here

But about List Register, they do not mention it as a banked register.

However i think it might be a banked register per physical core.

This is a capture of GICv2 specification about List Register. enter image description here

If whoever knows about if it is banked or not, please let me know.

Thank you previously.

Jeungwoo Yoo
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  • Have a look at `GICH_ELRSRn`. Apparently, the list registers are kind of hybrid. There's more than one available but they may be less than one per vCPU. – JimmyB Apr 04 '16 at 15:32
  • Firstly, thank you for your reply. but if `GICH_ELRSRn` means the number of List Register per core? It could be i think. – Jeungwoo Yoo Apr 04 '16 at 16:17
  • No, it is not banked. The virtualization extensions operated in **NORMAL** mode. The banked modes are for secure/normal world. – artless noise Apr 05 '16 at 14:10
  • Thank you for reply. And i want to ask you again about the exact meaning of "banked modes" what you mentioned upper reply. Thank you previously – Jeungwoo Yoo Apr 05 '16 at 14:13
  • 'banked modes' are secure and normal world (TrustZone); should be 'banked worlds'. There are several modes on ARM with banked registers, but the GIC banking is different. The terminology is confusing. You can switch worlds in 'monitor mode' using the **NS** bit of the SCR and [you will see the different copies](http://stackoverflow.com/questions/22080918/trustzone-monitor-mode-and-ifar-ifsr-dfar-dfsr). – artless noise Apr 06 '16 at 21:45

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