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I try to read the value of x86_64 register rip. Here is what objdump shows.

4017ec: 48 8d 35 00 00 00 00  lea    0x0(%rip),%rsi
4017f3: 41 89 d4              mov    %edx,%r12d

I expect that after instruction 0x4017ec is executed, the value of rsi should be 0x4017ec. However it is 0x4017f3, which is the address of the next instruction.

I use gdb to stop at 0x4017ec and at that time the value of rip is 0x4017ec. Why is rsi not loaded by the value of rip at that time? Should the processor read instruction from 0x4017ec?

Peter Cordes
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xywang
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  • Not sure if this is the actual reason, but I wouldn't expect the instruction to be executed until it had been read, which would presumably update the ip register to be after the instruction. – clstrfsck Nov 22 '15 at 06:35
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    IIRC, that's normal. During the execution of an instruction, `rip` points at the *end* of the instruction, i.e. the start of the next. This is the same as for jump and call instructions. The relative displacement is from the end of the `jmp` – Peter Cordes Nov 22 '15 at 07:53

2 Answers2

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rip always hold the address of the next instruction while running the current instruction. If fact updating rip by the address of the next instruction, is part of the execution process of the current instruction.

Mansureh Shahraki
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Depends on the architecture %rip holds either the current executing instruction or the next instruction to be executed. Here you added a breakpoint before 0x4017ec which means the next instruction to be executed is 0x4017ec. But %rsi will be loaded only after executing the first instruction. By then %rip would have already updated to point to the next instruction.

Anand J
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    Well some architectures other than x86 have PC / IP registers that hold the start of the current instruction while it's executing, but no other architecture calls it `%rip`. On x86-64, it doesn't depend on anything; it's always the start of the following instruction, because that's how it's defined to work in the x86 ISA. – Peter Cordes Nov 11 '16 at 21:28
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    On ARM (32-bit), PC is usable in addressing modes (or as a regular register). Its value is *2* instructions beyond the one executing. So this is a counterexample to the first sentence. You always need to check the architecture manual. – Peter Cordes Mar 06 '18 at 00:58