verilog instantiate multiple registers

Question

I have writen an 8bit register module like this:

module ff_8 #(
     parameter q0=0
)(
    input clk,
    input rst_n,
    input enable,
    input [7:0] d,
    output reg[7:0] q,
    );

always @ (posedge clk)
if (!rst_n) begin
    q <= q0;
end else if(enable) begin
    q <= d;
end

endmodule

How can i have multiple (128) instances of ff_8 each with different q0 parameter without having to write the same code 128 times?

Ok, but how should i declare the 128 parameters? As an integer array? — k k, Oct 09 '14 at 14:12
If your parameters are regular, e.g. 1, 2, 3..., you an use the genvar in your generate loop. Otherwise, define an array of parameters and index it with your genvar variable. See here: http://stackoverflow.com/questions/23507629/parameter-array-in-verilog — Ari, Oct 09 '14 at 20:55

score 0 · Answer 1 · answered Oct 15 '14 at 03:41

In SystemVerilog, you could create a module for the whole array of registers with the following:

module flop_array #(
    parameter int unsigned depth = 128,
    parameter int unsigned width = 8,
    parameter bit [width-1:0] q0[depth] = '{default:0}
)(
    input clk,
    input rst_n,
    input enable,
    input [width-1:0] d[depth],
    output logic [width-1:0] q[depth]
);

always_ff @(posedge clk)
if (!rst_n) begin
    q <= q0;
end else if(enable) begin
    q <= d;
end

endmodule

verilog instantiate multiple registers

1 Answers1