-5

I once did some tutorials on osdev.org and one interesting point was how the CPU is set into idle mode.

Because when no task has work to do you want to put the CPU into idle mode and not consume any current.

On x86 it is done like this:

JMP .

You might think this instruction will hang up the CPU making a hardware reset necessary (as expected). But instead it puts the CPU in idle mode.

Is this the only instruction or are there other instructions used in the past (on different CPUs)?

zomega
  • 5,362
  • 4
  • 25
  • 52
  • 7
    The question starts with a confidently-asserted false premise (again), and as far as the ISA is concerned, an actual halt instruction is not a particularly interesting one (Once you know the instruction is there, what can you really ask about it? Opcode number and mnemonic? That’s just an arbitrary assignment.), so I’m not seeing much value in this question. – user3840170 Dec 09 '22 at 20:13
  • @user3840170 Shall I delete it? – zomega Dec 09 '22 at 20:15
  • Now that it has an upvoted answer, I don’t think that’s possible. – user3840170 Dec 09 '22 at 20:36
  • 1
    You can delete your own question, whether it has upvoted answers or none at all. That happens frequently on SE. You'd be choosing to withdraw it from the site having assessed its answers and comments, which is your prerogative. Otherwise, OPs would be stuck with something they later change their mind on. Following its progress, I'd say it's the right move. – TonyM Dec 09 '22 at 20:59
  • I will leave it. I think it's normal that questions on SE sometimes contain false information. – zomega Dec 09 '22 at 21:09
  • Sure and that's your choice and prerogative as an OP. Unfortunately, it does mean that future readers of just the question can be misled if they decide not to flog through the comments or answers. – TonyM Dec 09 '22 at 21:11
  • 3
    Note that HLT didn’t actually reduce power consumption on x86 until the 386SL in 1991. Some earlier x86 CPUs could be powered down, but not using HLT. – Stephen Kitt Dec 09 '22 at 21:29
  • Sometimes questions based on a false premise can be useful and illuminating… but I don’t see a point of this one in particular. Like I said, a halt instruction is either present or not, and is pretty trivial otherwise from an ISA design standpoint. – user3840170 Dec 09 '22 at 22:30
  • @TonyM questions with an upvoted answer can’t be deleted by their author. – Stephen Kitt Dec 09 '22 at 23:01
  • @StephenKitt, thanks and I do stand corrected about the method though not the result. The OP cannot directly delete the question, they "must vote to delete and/or flag for mod attention" which is a request then assessed that can lead to the answer being deleted. – TonyM Dec 09 '22 at 23:13
  • One point - this is retrocomputing. As far as we're concerned, there are CPUs that are not x86 CPUs. The "not consume any current" part, even when interpreted not entirely literally, is not a feature of most of the CPUs we may be interested in. More specificity in questions would be appreciated, please. – dave Dec 09 '22 at 23:15
  • @StephenKitt IIRC the 80C86 goes down to >0,5mA when HLT is executed (Non-Halt current >50 mA). – Raffzahn Dec 09 '22 at 23:41
  • 2
    I think this should be closed – it's a list question, and not the good sort. I'm not sure which close reason would be appropriate for that, though. – wizzwizz4 Dec 10 '22 at 00:06
  • @Raffzahn AFAIK it goes down to 0.5mA in standby mode, which is when the clock is stopped; that requires external help, the 80C86 can’t stop its clock on its own. – Stephen Kitt Dec 10 '22 at 07:41
  • 1
    @wizzwizz4 that’s why there’s a custom reason ;-). – Stephen Kitt Dec 10 '22 at 08:32
  • 3
    I’m voting to close this question because it asks for list answers. – Stephen Kitt Dec 10 '22 at 08:33
  • @StephenKitt Now that's interesting, I checked the (Renesas) datasheet, and it explicitly states that 0.5mA is when HLT is executed (Iccsb on p.17 + footnote 7 on p.18). Since I trust your knowledge, I double checked with Intel and had to read that their 80C86 needs clock stopped (Iccs on p.9). So there are major design differences! (yes, that is major when it comes to battery powered devices) – Raffzahn Dec 10 '22 at 11:45
  • 2
    This question and its answers in general may be conflating "the system is idle" (not doing useful work) and "the cpu is idle" (not executing instructions). Do we have any evidence that any x86 CPU handles "jmp to self" specially? – dave Dec 10 '22 at 13:51
  • 1
    @Raffzahn that’s a significant advantage for the Renesas variant, on systems which use HLT! – Stephen Kitt Dec 10 '22 at 13:56

2 Answers2

7

Some CPUs have a "HALT" instruction that stops processing until a RESET or interrupt occurs.

It really varies quite a bit between CPUs. But the x86 processor is among those with a HALT instruction:

x86 HALT Another HALT - 8086

On a side note, I'm not sure I would call "JMP ." to be idle. This instruction forces the CPU into an infinite loop. HALT, on the other hand, literally stops processing.

On the other hand, the popular 6502 CPU has no halt instruction and there is no "software" way to halt it. Some use one of the BRANCH instructions after setting or clearing the appropriate status register bit or a JMP instruction with that instruction as its target. But until the 8086 HALT, the bus remains active.

The Z80 processor does have a HLT instruction and it behaves very much like the 8086/x86:

Z80 Halt

On a more modern note, the ARM CPU also has a HLT instruction:

ARM CPU HLT

TonyM
  • 3,704
  • 1
  • 19
  • 31
jwh20
  • 3,039
  • 1
  • 10
  • 19
  • So what I wrote wasn't right at all (oops). – zomega Dec 09 '22 at 19:45
  • 1
    The Intel 8008 already had a HLT instruction. – chthon Dec 09 '22 at 20:02
  • See this related answer on Unix.SE — Unix V1 already used a “wait” instruction. Modern x86 varies depending on the specific CPU. – Stephen Kitt Dec 09 '22 at 21:26
  • "But until the 8086 HALT, the bus remains active." Did you mean "unlike" here? – ecm Dec 09 '22 at 23:56
  • @jwh20 Your assertion that "the popular 6502 CPU has no halt instruction and there is no "software" way to halt it" is incorrect. Specifically opcode #$02 (HLT/JAM) is a 1-byte zero-clock 'undocumented' instruction which breaks the internal T-state counter, making it impossible for the CPU to complete the instruction and thereby terminating all activity. The only way to restart the CPU is to tickle the RESET pin. – Eight-Bit Guru Dec 12 '22 at 11:29
  • That may be the case but I was not referring to undocumented instructions. There are a number of undocumented opcodes and they are not consistent across all the variations of the 6500 family of processors. – jwh20 Dec 12 '22 at 12:17
0

It's not a question of not consuming current. It's a question of not producing any side effects. Many things you might tell the CPU to do would have side effects, and those side effects might be bad in some circumstances.

It's also a question of not disabling the interrupt system. In most early computers HALT or its equivalent not only stops processing, but it also disables interrupts. Interrupts are what enable the operating system to be event driven.

In the case of an operating system with no tasks waiting for CPU time, "jmp ." meets the need nicely. It doesn't produce any side effects, it can be interrupted between any two executions of the instruction, and also it doesn't take up much space.

Walter Mitty
  • 6,128
  • 17
  • 36
  • 'Many early computers'? I wouldn't know of any, especially not microprocessor based ones. Do you have any examples? Also, JMP * does have several disadvantages, foremost continuous memory access. – Raffzahn Dec 10 '22 at 12:55
  • OT - I googled 'null job'. It seems that there are null jobs out there that will pay $38k to $90k US per annum. – dave Dec 10 '22 at 13:43
  • @Raffzahn - the PDP-10 has HALT mean halt. As far as I recall. the null job is just a tight loop. Also, simh has 'idle loop detection' for many emulated CPUs, to reduce host CPU consumption when the guest OS is idling; this is circumstantial evidence that it's not uncommon for an OS to just loop in its null job. – dave Dec 10 '22 at 13:58
  • 1
    Yes, the PDP/10 HALT instruction (0) halts the system (WAIT, 1, waits for an interrupt and is the closest equivalent to the x86 HLT, and was used in Unix). – Stephen Kitt Dec 10 '22 at 14:04
  • 1
    Right. On PDP-11, HALT halts the system, WAIT pauses instruction fetch and gets the CPU off the bus. So the minimal null task is 1$: WAIT ; BR 1$. Generally, though, there's some rotate-the-lights work added in there. (I've never seen WAIT used except for the null task!) – dave Dec 10 '22 at 16:07
  • 1
    Ah, yes, that‘s the PDP/11 instruction set, not PDP/10. – Stephen Kitt Dec 10 '22 at 18:00
  • 1
    @StephenKitt - about the only thing those ISAs have in common is that I happen to have programmed in both :-) – dave Dec 11 '22 at 00:17
  • @another-dave Well, that HALT instruction is not really the same as the halting this questions asks about. It just bears a similar name. It's more like a 'left over' of times when machines were single purpose and intended to stop operation after that task - like a calculation - was exhausted. – Raffzahn Dec 11 '22 at 21:49
  • @raffzahn. I'm thinking of lots earlier than micros. I think the Univac 1 had a halt instruction. I'm pretty sure the IBM 709 and 7090 had one. The PDP-1 had one. I don't know about the Atlas. – Walter Mitty Dec 13 '22 at 18:38
  • @WalterMitty as mentioned, that's a different type of HALT instruction, just similar by name. Those early machines were designed to work like a programmable calcuator, performing a single job and halting when done. While using the same (or alike) naming, it's not about going into an idle state as the question asks. There are CPU supporting either or even both types of halting. Either by instructions or special registers (like the /360 has a PSW bit to go into and out of IDLE state, while HALT state can only be issues manually via the operator panel.) – Raffzahn Dec 13 '22 at 18:56