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I'm writing a PDP11 emulator. When CPU read odd address on Unibus odd address exception is launched. But the code below INC increments PRTPTR by 1 which make TSTB @PRTPTR generate a exception when it try access odd address. 

PRTAST:
    TSTB @PRTPTR
    BEQ 2$
    MOVB @PRTPTR,@#177566
    INC PRTPTR
    RTT
2$: CLRB @#177564
    RTT

How MOVB and TSTB and all byte instructions work with odd address?

Fabio
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1 Answers1

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As far as the Unibus is concerned, all reads are word-sized (and from an even address), and the CPU simply ignores the portion of the word it wasn't interested in. Thus, to read an odd-address byte, the CPU reads the even-address word containing that byte, and uses only the top 8 bits of the result.

Unibus writes are allowed to be byte-sized (there are 2 separate write cycle types: DATO and DATOB, which correspond to word-write and byte-write respectively). Word writes are always to even addresses, but byte writes may specify an odd address. Note however that for a byte written to an odd address, the byte value must occupy the upper 8 bits of the Unibus data lines (i.e. it can be thought of as a word write with the lower even byte masked out). To put it another way, for a DATOB byte write cycle, the lowest address bit is treated as a flag indicating whether the byte of the Unibus data word that is intended to be modified is the upper one, or the lower one.

Q-Bus works the same way -- reads are always word-sized, and writes may be either word or byte sized, with byte-sized writes using the upper or lower byte depending on whether the address is odd or even.

Ken Gober
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  • Does Q-Bus work exactly the same for word and byte access? – RichF Jan 05 '20 at 21:57
  • Yes, although the actual bus signals used are different. I suppose I should have mentioned that, even though the original question referred to Unibus explicitly. I'll edit that in, thanks for bringing my attention to it. – Ken Gober Jan 05 '20 at 23:34
  • TSTB @PRTPTR is a DATI cycle Unibus. When @PRTPTR is odd DATI fail or not? Is DATI with odd address permitted? – Fabio Jan 06 '20 at 00:08
  • @Fabio DATI is a read cycle. So the whole word is read over the bus and the CPU ignores the irrelevant half. – Chromatix Jan 06 '20 at 07:18