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Hello I am asking here because I do not see a general firmware Stack Exchange or better place. I am open to suggestions on that.

But my question is pertaining to Intel Atom SoCs. I am interested in when the processor resets, then the BSD executes instructions from 0xFFFFFFF0 which is 16 bytes below the 1 MB limit in real mode. What should my firmware do at this point, I think it should perform a jump to somewhere that the BIOS/firmware is mapped to. Basically can someone map out the 16 MB Spi flash ROM to logical addresses on the SoC.

Helmar
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marshal craft
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    Hello and welcome! I am not sure if this is / should be on-topic here. Maybe http://electronics.stackexchange.com/ is a better fit. – Ghanima Jan 04 '17 at 22:29
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    Welcome to the IoT.SE. I checked briefly with the EE guys and it might be on-topic there. You might want to provide a bit more information though, because the question didn't seem too clear. Meanwhile we can discuss on [meta] if we consider questions like this on-topic here. – Helmar Jan 04 '17 at 23:20
  • For the time being I would like you to elaborate a bit more, what exactly you want to know, the question is a bit unclear to me. – Helmar Jan 04 '17 at 23:26
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    Related meta discussion: http://meta.iot.stackexchange.com/q/178/54 – Ghanima Jan 04 '17 at 23:32
  • Are you writing the ROM code? That's not clear from your question. What do you mean by “map out the 16 MB Spi flash ROM to logical addresses”? Logical addresses are up to the MMU configuration, and if you're writing a bootloader at any stage then it would be up to you to set up the MMU. Are you asking about the mapping to physical addresses? That would make sense but the answer should be in your datasheet. – Gilles 'SO- stop being evil' Jan 05 '17 at 00:54
  • It is the spi flash rom. A flash rom that is writeable in 4k byte blocks. I have searched the atom data sheets. The spi interface is located in the processor control unit. This spi interface is souly for the bios/firmware and not the regular spi io which are separate gpio pins. When the processor boots it selects a boot strap processor which begins programed execution at code segment f0000h. Instruction counter ffff0h. This I think I know has to be the beginning of the second 4kbyte block on the spi flash rom. But once the IC goes up 16 bytes I think it will get an error because there – marshal craft Jan 05 '17 at 06:42
  • Is 1 megabyte limit in real mode. – marshal craft Jan 05 '17 at 06:42
  • @marshalcraft Welcome to the site! Consider editing all the extra details into your question so it's clearer (comments aren't easy to find or search), and I wish you good luck in finding your answer! – Aurora0001 Jan 05 '17 at 15:52
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    See here: https://superuser.com/questions/988473/why-is-the-first-bios-instruction-located-at-0xfffffff0-top-of-ram – ceving Jan 03 '18 at 14:51
  • It's been a while, I haven't been able to have time to deal with these things, but I vaguely remember being able to find an example binary rom file and being able to find the x86 opcode. So I guess that would be a form of reverse engineering an answer. Not really the best. I would like a general answer for most intel chipsets, about writing the flash descriptor. Or if this is not how its done, I really wish there was a good explanation of the bios build process. Could be the intel bios compiler does this stuff, making it opaque to the developer. Sime cpus have chipsets, the socs don't etc. – marshal craft Feb 03 '21 at 11:06
  • The x86 jump which would be mapped to the 0xff...0 address. I don't remember, but presumably the address which is jumped to, should reveal some extent how rom memory is mapped. – marshal craft Feb 03 '21 at 11:09

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The firmware should jump to a routine that reads the second stage boot loader into RAM and then execute it. To map the SPI in the logical memory space the SoC would have to support this internally.

The question is not out of place here, but you can always ask hardware related questions at Electrical Engineering.SE.

Aurora0001
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  • Thanks I haven't been at home long enough to ask at electronics. Seems to me a general firmware or even a x86 and ARM firmware's stack exchange would be nice. The NVRAM is not yet available. The SPIis mapped as the first instruction is at code segment 16 bytes below the the 1 Mbyte limit in real mode from the cpu's perspective. That first opcode byte is a location on the SPI flash. My problem is I do not know where it should be. At this point I am beginning to believe it is different for different intel cpu. – marshal craft Jan 06 '17 at 06:50
  • I have read for atom e3800 that it should be right after the 4kbyte block so spi flash address 0xF9F plus one. I have read else where that it should be the last address of the supported flash size in non descriptor mode. In any case does somebody know the one to one map of a processor address to the spi flash? Maybe I will try asking on intel forum. Also I'm aware some stuff is confidential but also some stuff has been released from it's confidentiality or is readily observable on spi flash so maybe somebody knows. If I find out and am not under nda I will answer the question as it help others – marshal craft Jan 06 '17 at 07:00