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I need help in the layout of an ethernet interface (ESD protections + RJ45 connector). The connector I would like to use already has built-in magnets, so I only have to connect the ESD protectors.

Almost all ethernet ESD protection chips have this package and pinout, see the example the ESDS312DBVR.

My doubt derives from the fact that in the datasheet of the ethernet controller it is recommended to trace the differential pairs towards the RJ45 connector all on the top layer; while the ESD protection datasheet instead recommends changing the bottom layer:

enter image description here

https://www.ti.com/lit/ds/symlink/esds314.pdf

What would be the most correct way? I think it's best to avoid vias, so do everything on the top layer, but then I'm having trouble connecting ESD protection.

My idea is to use two ESD protection chips, one for the TX pair and one for the RX pair (so using only half a chip and two hips) and going under the chip with the differential pair might be a solution? What do you think? This way:

enter image description here

Federico Massimi
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  • Why not use the ESDS312 which is a dual chip and route via unused pins? If you use two quad chips then you have just dual protection. – Justme Apr 11 '23 at 09:51

1 Answers1

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Using a two chips, one for each pair would be fine.

In the case of the chip you show, routing the pair underneath an presumably unsoldered pin as you show is not a good idea.

I would instead either rotate it 90 degrees and running the pair down the centre between the pins, with some very short stubs sticking out to the pins (red), or run through both sets of IO pins with the trace (blue) - in fact on reviewing the ESDS312, this is exactly how it's designed with the two NC pins being allowed to be connected for straight through routing.

Routing under chip

Alternatively you could choose an ESD chip better suited to differential pairs, such as the TPD4E05U06 or similar package device.

Layout of TPS4E05U06

Image from datasheet

Tom Carpenter
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  • I would like to avoid using the TPD4E05U06 because it has a very very small package and is difficult to solder. If there are no contraindications, I prefer to use two "half chips". – Federico Massimi Apr 11 '23 at 09:30
  • Using a quad for two lines, better to wire pins 1 and 6, and 3 and 4, to each line, so the pair flows across the chip, symmetrical around GND. – Tim Williams Apr 11 '23 at 09:43
  • @TimWilliams doubling up is probably not ideal. But looking at the datasheet for the ESDS312, the second pair of pins is N/C for route through so ultimately you're correct about the direction of routing. – Tom Carpenter Apr 11 '23 at 10:02
  • @TomCarpenter Can you explain how it isn't "ideal"? – Tim Williams Apr 11 '23 at 11:33
  • @TimWilliams extra loading capacitance. Probably won't make much difference for ethernet I suppose. Could cause problems for higher frequency buses like HDMI and USB3.0. – Tom Carpenter Apr 11 '23 at 13:19
  • Good point. This part has relatively high capacitance, so it would be adequate for up to GB Ethernet (< 100MHz BW), as it shows -3dB at ~900MHz for a single ... actually they don't specify what, but I assume a single pair used differentially? Two in parallel would then be 450MHz, which is still plenty, and might be marginal for USB High Speed. A lower capacitance device would be needed for faster speeds. – Tim Williams Apr 11 '23 at 14:34
  • I found an application note of Ti about ESD312, anche they use the sceme 1/6 and 3/4 proposed by @Tim Williams, Probably this the best solution. – Federico Massimi Apr 11 '23 at 15:25
  • @FedericoMassimi I agree - this would be wired as per the blue lines in the first diagram. – Tom Carpenter Apr 11 '23 at 15:29
  • @TomCarpenter: maybe could be better use this chip: 82400102 wurth electronics, that has the same pin mapping but single load capacitance. – Federico Massimi Apr 11 '23 at 15:36
  • @FedericoMassimi The 312 should be fine as that only has two IO pins (the others are NC). It's the 314 that would potentially have a double loading issue (I didn't checkt he datasheet closely enough when I first answered the question). – Tom Carpenter Apr 11 '23 at 15:50