I am currently struggling with the following challenge.
In the system I am currently designing, the transmitting device is equipped with an image sensor with MIPI output (1 data line, 12 Mbit data rate). The camera is configured to send data practically all the time - its duty cycle is about 95%. The data is converted from differential voltages to single ended by using a high-speed comparator. This signal is wirelessly transmitted to the receiver.
The transmission path works seamlessly, i.e., the received signal is the same as the transmitted signal.
My challenge is to recover the clock line from the data line. For this purpose I plan to use PLL.
The first question is about using a phase detector - which one to use:
A type I detector (XOR gate) has the advantage that when there is no signal, the frequency returns to the center frequency, which I can set so that it is practically the same as f of the clock - thus the clock will not 'run away' to another frequency during a temporary lack of data. On the other hand, I found information that the input signal should have 50% duty cycle - and such a fill will definitely not be there because it is data.
The type II detector supposedly doesn't have to have 50% fill of the input signal, but for that during the absence of a signal its frequency returns to f min - which can be a problem during short data interrupts.
The second question is whether I should still prepare the signal somehow. In one place (link) I found information that I should use a circuit that detects edges and generates voltage pulses in their place.
Edit:
- What components are you able to build your circuit with? Can it be from any required ICs, just an FPGA or something else?
I would like to do it with as little effort as possible. I started working with PLL because it seems to be the simplest solution. If anyone recommends an off-the-shelf IC I would be happy to use it.
