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I'm trying to make a video timing generator on an FPGA. I'm finding a difference online in the order this occurs:

Here's one version: enter image description here

and here's another: enter image description here

Where this seems inconsistent: If scanning from left to right, top to bottom, does the vertical front porch occur immediately after the horizontal back porch or the horizontal sync? Likewise, after the vertical back porch has ended, would the next pixel be active video, or part of the horizontal back porch?

Sittin Hawk
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    those are both the same ... the video signal is one long serial data stream ... the display folds the stream to cover the screen ... https://www.causewaysecuritysolutions.com/uploads/1/6/8/8/16884516/1731451_orig.jpg – jsotola Apr 01 '22 at 15:17
  • think of serial communication ... the start bit comes before a data byte but it also comes after the previous data byte – jsotola Apr 01 '22 at 15:23
  • @jsotola I'm standing by my original question that they are not the same. Again, focus on the transition right at the end of the vertical back porch. Is the next pixel active-video or horizontal back porch? It can't be both – Sittin Hawk Apr 01 '22 at 15:33
  • here is a diagram of the vertical sync ... http://2.bp.blogspot.com/-QdO2J14-Ig4/UN7JEflmloI/AAAAAAAAEho/oUzsumrQEV4/s1600/ntsc.gif ... the H-sync is maintained throughout the V-sync interval ... video signal is supressed – jsotola Apr 01 '22 at 15:48
  • @SittinHawk Can you indicate, with a clear marker on your actual image, which signal transition you're asking about? I see no discrepancy in the actual signals that are being transmitted, only that one definition overlaps the front/back porches and the other does not - this is of course completely moot because front/back porches are a method of accounting/timing the expected signal, and not actually an observable state of the video signal. – nanofarad Apr 01 '22 at 16:07
  • Looking closer, there are two separate possible questions here and it's confusing which one you're asking here. Are you interested in the discrepancy of the porches (which are only for accounting time and not observable), or are you interested in the discrepancy of whether VSYNC and HSYNC are deasserted together at the same time? Or something else altogether? – nanofarad Apr 01 '22 at 16:24
  • @nanofarad. I've updated the images to show where I'm confused. I'm just trying to understand exactly what is the correct sequence of events in terms of the zones so I can generate that sequence in the code. In one case, right when the vertical back porch ends, I'm immediately in the active pixel region, and in the other case, I have an extra horizontal back porch. I'm viewing time as going left to right (inner loop) top to bottom (outer loop), and then wraps back around. – Sittin Hawk Apr 01 '22 at 17:25
  • @nanofarad. Maybe I understand your point: So if the porches have no observable state, then it really makes no difference which point I'm calling the "end"? As long as the HSYNC and VSYNC versus active pixel timings are maintained, then both diagrams will work (even though they are technically drawn differently). So I can write my code to match either one, and it should work. – Sittin Hawk Apr 01 '22 at 17:39
  • @SittinHawk Yeah, I think we might be on the same page now. The period after the end HSYNC on the last line before the upper left corner of the active video is part of horizontal back porch (but not vertical back porch) on the first image, but is included in both back porches on the second image. The second image has the vertical front porch starting slightly earlier as well, but the relative timings from active video to hsync are the same. There's still a possible discrepancy with vsync, but my suspicion is that the two go to separate sync circuits and the difference may not be relevant – nanofarad Apr 01 '22 at 18:00
  • The context depends on for which display, or, for which display interface. If you have standard interface, or a display module with a datasheet, you can just use the standard formats or whatever the display datasheet examples give. Can you give more information about the display panel or interface?However, a very good approximation is that which ever sync polarity is used (rising edge or falling edge), the sync signals go active at the same time. – Justme Apr 01 '22 at 18:58

2 Answers2

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These images are deceiving: they are drawn flat, but topologically they are depicting a surface of a torus (a donut with a hole in the middle).

The right edge connects with the left edge. The top edge connects with the bottom edge. The rectangle you used to view the flattened surface of this torus can be located arbitarily - only its orientation is fixed.

So the images are just two different "flattenings" or projections of the same torus.

Another way to view this is to extend the images by repeating them infinitely horizontally and vertically. Then you can move the viewport anywhere you want and it's still showing the surface of the same torus, just at a different horizontal and vertical offset.

I've extended the first image in your question in a torus-like fashion, and outlined the second image you posted. As long as you can do such a transformation, both are equivalent!

The 2nd torus projection stitched from the 1st projection

Kuba hasn't forgotten Monica
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The difference seems to be simply that the (imaginary, externally non-observable) periods of time for the horizontal and vertical porches are counted differently. In the first image, the period between HSYNC and the first active image pixel (3-4) is considered part of the vertical back porch:

enter image description here

while in the second image that same (equal-length) time period from hsync to first active image pixel (3-4) is considered part of the first line outside of the back porch:

enter image description here

Essentially, the vertical back porch starts, and ends, earlier in the second image. However, the disagreement occurs outside of the active area and sync signals anyway, so there is no real timing discrepancy.

The two images still have an unclear discrepancy with when the VSYNC signal starts and ends, since they don't have enough detail to show relative timing between HSYNC and VSYNC. The ambiguity is whether VSYNC starts with the horizontal back porch, through the end of the vertical back porch, or if it starts at the end of the horizontal back porch and ends at the end of the horizontal sync. On the diagrams, this can be seen as a discrepancy of whether (1) aligns with (3) or with (4).

A few references I looked at (including ones that reproduce diagrams from monitor manuals) also don't show this relationship, and display timings are generally a mess of different competing standards with vague similarities and subtle differences.

I would suspect that because these drive separate sync and counter circuits, that exact relationship doesn't matter as long as the general timings (line-to-line and column-to-column) match up.

nanofarad
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  • It sounds like a good analogy is left justified vs centered in terms of representation of the same datastructure? – crasic Apr 01 '22 at 18:15
  • @crasic Potentially - I'm personally not seeing the analogy since I might have a different model of what I expect when talking about alignment in a data structure/struct (and the sync discrepancy is an extra complication) – nanofarad Apr 01 '22 at 18:17
  • @Kuba captured the "torus geometry" that my analogy was pivoting from, both of your answers helped me learn a lot! – crasic Apr 05 '22 at 01:09