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Currently I am trying to learn more about computer architecture. I seem to understand the concept of sequential circuits but there is one thing I cant understand and I cannot find any info on it

Lets say we have a Latch with NAND gates, my question is specifically on the part where the ouputs feed into inputs. There are 2 inputs required for there to be an output in a NAND gate. I cant seem to get my head around how both the NAND gates get their second input when that input comes from the output of the other gate, but to get this output we need 2 inputs. This is the loop being played around in my head.

Is the default value 0? Does one of the NAND gates get its output first?

Please let me know if I should rephrase this question

Coding
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  • Hmm, rephrasing might be a good idea, maybe with a schematic and timing diagram. I'm not sure I understand your question as it's stated. – John D Dec 09 '21 at 23:58
  • If you can post a schematic that would help make sense of what you're trying to say. – TimWescott Dec 10 '21 at 01:25
  • The initial value of a latch on power-up doesn't matter, because you design the system in such a way that the latches are initialized with known data before you use them for anything, if that's what you're thinking of. – Hearth Dec 10 '21 at 03:19
  • An exact explanation requires an exact schematic. – Andy aka Dec 10 '21 at 09:29
  • Sorry for not posting a diagram. I'm new to this side of stack oveflow. – Coding Dec 10 '21 at 20:01
  • Thank you td127 for the clear explanation as well as the corner cases I need to know – Coding Dec 10 '21 at 20:20

1 Answers1

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If I understand your source of confusion, you are wondering about the apparent “chicken and egg” situation of a combinatorial circuit with feedback.

For example, with a NAND latch how can we determine Q if it depends on Q’, which in turn depends on Q? Is there a default value? Does one of the NAND gates get its output first?

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In this particular case, it is true that the NAND gates have two inputs, but the nature of NAND gates is that if either input is low then the output is high. So if S’ goes low then Q will go high, regardless of anything happening on the other input – there is no race condition or infinite loop. Same thing if R’ goes low: Q’ will go high, period.

But there are two problems with this circuit that make your concerns justified.

First, is the initial condition: you can’t make any assumptions about the state of Q and Q’ on power up – they are unknown. And as long as S’ and R’ stay high they will remain unknown. Bringing either S’ or R’ low will stabilize the outputs to either 10 or 01, and it is expected the system design will do this. But if S’ and R’ boot up high, then not only are the outputs indeterminate, they could actually oscillate: if the delays through the gates were perfectly matched then if Q and Q’ happen to boot up 00 (and S’ and R’ are 11) then both Q and Q’ will go to 11 at the same time, which will then reach around and cause Q and Q’ to both go to 00, and repeat. The frequency of oscillation is determined by the gate delay. In real life the delays won’t be identical and the outputs will likely eventually settle at a stable 01 or 10 but you won’t know which.

The other problem is if both S’ and R’ are 00, which cause Q and Q’ to go to 11, and then both S’ and R’ change to 11 simultaneously: we are back to the same situation as above and will likely oscillate or at least go to an indeterminate state. A system designer should avoid doing this.

So the moral is, you do need to be careful using feedback in combinatorial circuits – they can oscillate or have race conditions – but as long as these corner cases are understood they can be avoided by proper system design.

td127
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