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Does anybody know if a "PCI riser card" generates a local PCIe clock on the riser board that is asynchronous to the PCI clock on the Motherboard, or does the PCIe clock come only from the adapter cable that plugs into the PC motherboard (blue USB cable with 1x pcie connector for PC motherboard)?

the reason why i'm asking is because I was curious if I could use a riser card to plug in a "Xilix FPGA card with PCIe edge connector" to obtain a PCI Clock, Specifically, without pluging in the USB-like cable to the PC motherboard PCIe slot to get the PCIe clock from the motherboard.

I'm hoping there's a PCIe bridge chip sitting on the riser card, with a local pcie clock generation circuit... is that the way a riser card works? Anybody know where I can find a schematics of a typical riser card?

PCIe riser 1 to 4

Bill Moore
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  • This is not a standard product, and it's highly unlikely that it follows the PCIe spec closely given the hacks in place. You'll need to inspect it yourself to determine what ICs and other components are onboard, and then determine whether any of them independently generate clocks without being connected to a root complex. The reference clock can just as easily be generated for each link as well as buffered, and even if it's generated onboard, that might only occur when the board is connected. – nanofarad Jan 14 '21 at 18:39
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    Questions on use of electronics are off topic. There is no requirement for PCIe devices to share a common reference clock, so whether or not that board distributes the clock from the motherboard or generates its own is not determinable without either a schematic (highly unlikely to be available), or reverse engineering (not possible from a photo). – Tom Carpenter Jan 14 '21 at 18:42
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    This is just standard crypto-currency equipment these days... Surely somebody knows what the schematic of such a simple card looks like without actually buying one to inspect it.... – Bill Moore Jan 14 '21 at 18:47

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Using the reference clock on the PCIe connector is pretty much optional, the actual clock is recovered separately for each lane and the only requirement is that parallel lanes are derived from the same base clock so data can be interleaved and de-interleaved reliably.

The USB cable has one transmit and one receive pair, and no separate clock connection exists.

The card must contain a PCIe bridge to allow all slots to work, and that bridge IC will have to recover the link clock in order to receive data. Whether it reuses that clock or generates its own for the downstream connections is unspecified.

The bridge IC contains clock domain crossing FIFOs anyway to allow device-to-host and device-to-device communication so there is no way to tell whether powering this device would generate a clock and feed it to an FPGA board.

Since your FPGA board should have an independent clock source anyway (the state machines for link training need an independent clock), I suggest you use that one and run it through a PLL to generate the frequency you need.

Most likely this will be some 40 or 50 MHz source, so you can easily derive 100 MHz from it with good stability.

Simon Richter
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    For what its worth, the PCIE core that comes with Xilinx Vivado 2020 doesn't allow the use of an internally generated PCIe reference clock, The rational they provided for this is that the clock needs to be more accurate then what the FPGA can guarantee, therefore the reference clock needs to come from the board instead... However, without plugging the Xilinx Card into a PCIe slot, you don't have a clock to run the PCIe logic core...It will just hang the internal AXI buses connected to the PCIe core, and will not provide access to any registers of the PCIe core... – Bill Moore Jan 14 '21 at 19:53
  • Based on what you are say, I guess its safe to assume the riser card generates its own reference clock to be PCIe compliant, and this reference clock might be asynchronous in phase to the Root complex reference card, but that doesn't matter because the clock is recovered anyway from the data transitions of the PCIe packet in the Phy at the receiver... what is more important is the accuracy of the clock..so the spacing of the bits is identical between transmitter and receiver phy (+/- a constant period of one bit)... – Bill Moore Jan 14 '21 at 19:56
  • Good point about USB cable... only two differential pairs for TX, RX data and no possibility to send clock... – Bill Moore Jan 14 '21 at 20:04
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    @BillMoore, what is your goal here? What do you expect to happen when you activate the PCIe HIP core with nothing connected to the PCIe bus? – Simon Richter Jan 14 '21 at 21:49
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    I mean, a card that has not received it first CfgWr request to set the Enable flag in the PCI status register is neither supposed to talk to the bus nor does it know its own address. The PCIe core cannot do much without a bus connection. – Simon Richter Jan 14 '21 at 22:10
  • USB cables have three pairs - their's the D+/D- pairing which could be used for a clock. Although I guess that would probably be used for the PERSTn signal. – Tom Carpenter Jan 14 '21 at 22:24
  • Simon, Its because 'm writing new code and don't have anything to plug the FPGA card into... I want the logic i'm testing to run synchronously to the PCIe core clock... but, of course, now i know i can just buy a cheap PCIe riser card and use it as an FPGA card stand and get a clock to drive the FPGA as well.. At this point I'm ok with the PCIe core not connecting to anything. – Bill Moore Jan 15 '21 at 21:14
  • @BillMoore, I'd still expect the FPGA card to have an independent clock anyway, check its handbook. That might be more reliable than depending on an external board that may or may not derive its clock from yet another external board. – Simon Richter Jan 15 '21 at 21:26
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The riser card will include a clock buffer to redistribute the PCIe clock.

While a PCIe endpoint can recover its own reference clock from the incoming RX stream, this capability is optional, and not guaranteed to be supported by any given endpoint. In fact it's rare for an endpoint to not require a reference clock. This includes other uses of PCIe, such as NVMe cards and U.2 form-factor drives.

Note that the reference clock is different from the RX SERDES clock, which is indeed recovered from the data stream, aligned using a delay-lock loop. The reference clock is for the rest of the system upstream of the SERDES: it ensures that the endpoint FIFO behaviors are known. The TX side uses reference clock to make the transmit SERDES clock, regardless of whether it is supplied as a separate pair or recovered from the RX SERDES.

hacktastical
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