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I'm trying to design a startup network for this flyback controller, see the picture at the end. I want the controller to start within 10 ms at most. This is what I'm doing:

Due to the wide input voltage, I'm connecting the startup network to a tapping point from the capacitors in series. This allows me to choose a lower Vds depletion MOSFET like this: CPC3980ZTR

1) Would this cause some imbalance in the caps?

Now, during startup a current flows from inputs caps C14 & C15 through the depletion MOSFET Q5 (normally on). This current will charge the Vcc capacitor C16. The gate of Q5 is connected in the middle of the resistor divider formed by R29 and R30. As the voltage over C16 increases, the gate voltage of Q5 becomes negative with respect to its source voltage. When threshold voltage of Q5 is achieved, it turns off.

Resistors R29 & R30, and Zener diode D16 are dimensioned so that Vcc achieves the minimum value UVLO for the controller to start. From this point, controller will be fed by the auxiliary winding, and Q5 will stay off until the next start-up.

According to the datasheet, the threshold voltage for Q5 has minimum and maximum levels of -3.1 and -1.4, respectively. The minimum Vcc voltage for the controller to start is UVLO = 21V, and the max Vcc is 35V. I will allow a max voltage of 27.5V for overvoltage protection. During startup, the voltage over resistor R29 is the voltage between gate and source of Q5.

  1. By setting R29 = 10K
  2. R29*i_R29 < 1.4V only if V_C16 > 19.5V --> i_R29 < 0.140 mA for V_C16 = 19.5V
  3. R29*i_R29 > 3.1V only if V_C16 < 27.5V --> i_R36 > 0.310 mA for V_C16 = 27.5V

By using a 20V Zener diode as D16, the first condition is met.

For the second condition, the current through R29 can be calculated as

  • I_R29 = (V_C16 + V_D17 – V_D16)/(R29+R30)
  • R30 < (27.5 + 0.3 – 20)/(0.4mA) – 10K
  • R30 < 15.2K
  • R30 = 10K

2) How do I calculate a proper value for C16? And the time this circuit will actually take to start the controller?

enter image description here

EDIT: Below there is a potential way of doing it with a known current

enter image description here

1 Answers1

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1) Would this cause some imbalance in the caps?

Yes, but not significantly over the time period and current draw you are considering.

2) How do I calculate a proper value for C16?

This can be calculated using equation 9 in section 8.2.21 of the datasheet. It is dependent on IC operating current (including Gate drive output) as well as capacitor charging current and time taken for the auxiliary voltage to take over (which is determined by converter output current and capacitance).

And the time this circuit will actually take to start the controller?

Probably Longer than you want. The formula for capacitance when (dis)charging at constant current is \$C = i * t / V\$. Assuming the minimum charging current of 140 uA, 2.3 mA operating current + 1 mA Gate drive current, 9.35 V between VDD turn on and off, and 10 ms before the auxiliary voltage takes over, the capacitance required is (2.3 mA + 1.0 mA - 0.14 mA)* 10 ms / 9.35 V = ~3.4 μF. But if you use this value it could take ~1.8 seconds to charge the capacitor to the maximum startup voltage of 23 V (actually even longer, because the divider capacitors will 'unbalance' significantly over this time period).

To get the charging time down to 10 ms C16 must be no more than 140 uA * 10 ms / 23 V = ~61 nF, but this may only hold the voltage up for 61 nF * 9.35 V / 3.16 mA = ~180 us. So the controller will have to start up and charge its output capacitor in less than 180 us once the VDD turn on voltage is reached. This time adds to the total start up time, so to get a total startup time of no more than 10 ms the charging time must be even less.

To achieve your desired startup time you will probably need a much higher charging current.

Bruce Abbott
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  • So would I need to come up with a circuit directly connected to the bus voltage instead of the tapping point to achieve higher charging current? –  May 25 '20 at 22:28
  • That is the easiest option. You would need a higher current FET to handle the higher current. To reduce running power consumption you could use the circuit in figure 20, or perhaps use a PhotoMOS 'relay' to switch the charging resistor. – Bruce Abbott May 25 '20 at 22:46
  • Higher voltages Depletion MOSFETs are hard to find. Also, I need to define how much current I actually need. That's the confusing part for me, saying that "I need higher current" but how much it is what matters for the calculations. –  May 25 '20 at 22:50
  • Using the capacitor formula, solve for i, eg. 1uF * 23V / 5ms = 4.6mA. But this is just one of several problems to solve. I simulated your circuit in LTspice, and it didn't look good. The FET did not turn fully off, so the capacitors eventually became grossly unbalanced. I didn't even consider the converter itself, which should also be simulated to obtain its startup time etc. You may have to rethink your requirements because getting the startup time below 10ms from 100-600VAC with very low running power loss could be quite difficult with this circuit topology. – Bruce Abbott May 26 '20 at 05:44
  • There should be other ways or circuits to achieve this. It doesn't have to be the one I proposed. I will continue researching then. Maybe another approach using an enhancement FET instead of depletion. –  May 26 '20 at 12:24
  • I have edited the post adding another way of doing it. What do you think? –  May 26 '20 at 15:18