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I have a question about ESD effect on MCU pins that troubles me. MCU pins configured as input, that are not pulled low or high are likely to make trouble, and very likely to make trouble in case of an ESD pulse.

But what about:

  • MCU pins configured as tri-state?
  • MCU pins configured as output?
  • Would it make a design more robust to configure unused MCU pins as output?
Toby Jaffey
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JakobJ
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1 Answers1

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  1. Pins configured as "tri-state" are inputs.
  2. Pins that are actively driven high or low are at a low impedance, which makes them less susceptible to ESD. Outputs driven low are one case of that, so yes, that is a good thing to do with unused pins.
Olin Lathrop
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  • Every Pic datasheet I have ever read recommends driving unused pins low for this reason, and I believe that is generally the restart state of the TRIS and PORT registers. – captncraig Apr 05 '12 at 18:54
  • @CMP The restart state of the TRISx registers is as input. – m.Alin Apr 05 '12 at 19:42
  • Interesting. Any insights to why, when they also recommend driving them low if unused? – captncraig Apr 05 '12 at 20:33
  • @CMP Check out the answers to this question for some insight – m.Alin Apr 05 '12 at 21:56
  • @CMP: It makes sense for the pins to wake up in the most benign configuration for any external circuit. That is high impedance and to tolerate being driven to arbitrary voltages within the legal range. They can't know what pins you consider unused. Only you know how you're using the pins, so it's your job to set them up appropriately. That includes doing reasonable things with unused pins, like making them outputs and driving them low. – Olin Lathrop Apr 05 '12 at 22:07
  • Just to make sure I understand the details, driving the pin low directs the ESD pulse to GND, keeping the pulse from reaching the core? – JakobJ Apr 06 '12 at 06:14
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    @Jakobj: There is a FET in on state between the pin and ground, so most of the current should flow there where it can be properly handled. The on resistance of the FET also lowers the impedance of the line. This forms a voltage divider with the unavoidable capacitance between the line and the multi-kV pulse. The lower the impedance, the more this pulse will be attenuated and the lower the voltage spikes, which in turn cause lower currents in potentially bad places. – Olin Lathrop Apr 06 '12 at 11:07