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I want to use PCIe with four to eight remote devices, and preferably to avoid PCIe switch. In PCIe connector i can see enough lanes for that, but i definitely don't want to use eight separate cards for that. So one way is to put there a switch, but actually maybe i could just connect to the lanes separately?

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    A PCIe packet is, AFAIK coherent on channels. So you'll need a logic device / ASIC that uses IO Virtualisation to present any number of physical devices on the same PCIe bus. But I could potentially be wrong. – Asmyldof Mar 05 '16 at 21:38

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PCIe does autonegotiate the number of lanes to use on device initialization, but I do not believe it is possible to sudivide a single PCIe slot to connect to multiple devices without help from the upstream device (root port or switch). Some motherboards allow x16 ports to be reconfigured as x8 ports. Part of this is the physical reassignment of signals (done with high speed multiplexer chips on the board), part of this is in the configuration of the upstream root port or switch chip. The upstream device has to support splitting the lanes into multiple independent interfaces, and it has to be configured to support the lane configuration you want. Assuming the necessary hardware support is present, you may need to modify the BIOS to configure the lanes correctly during board-level initialization. You're probably going to be much better off if you use a PCIe switch. It should be possible to get a PCIe switch that will give you 8 1-lane ports on one side and a single 8 lane port on the other side. You may need to provide a small EEPROM chip that the switch will use to configure itself with the ID numbers and port configuration you want.

alex.forencich
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  • tl;dr: eight lanes share one transceiver block, but for eight links, you need eight transceiver blocks. – Simon Richter Mar 05 '16 at 23:34
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    I don't think transceiver block is quite the right word. In my mind, 'transceiver block' refers to a set of one or more SERDES blocks. You need one SERDES per PCIe lane, but that could correspond to less than one transceiver block if the blocks contain more than one transceiver. For example, in a Virtex 6 FPGA, the high speed GTH transceivers come in groups of 4 called quads. So one transceiver block (quad) could give you 4 lanes of PCIe. Now, the only thing the quads share is a reference clock, so that could be 1 4 lane interface, 4 1 lane interfaces, 1/2 of an 8 lane interface, etc. – alex.forencich Mar 06 '16 at 01:21
  • Yes, maybe a better term for the upper layers is needed. – Simon Richter Mar 06 '16 at 20:04
  • Yeah. PCIe interface, PCIe controller, and PCIe endpoint all might work, but I am unsure if some of these already have other meanings in the context of PCIe. There is probably a term in the standard. – alex.forencich Mar 06 '16 at 20:35
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    Just checked the PCIe gen 3 standard. Seems like the proper term is 'port'. The upstream device will support some number of lanes that may (or may not) be subdivided into groups which form ports. The device may only support a small set of port configurations, and it may not be flexible enough to turn specific lanes into individual ports. And this configuration would most likely have to be done at bus enumeration time. – alex.forencich Mar 06 '16 at 20:47