I studied electronics in a far away past and have sadly forgotten quite a lot. I was wondering what a signal to an 8 bit CPU looked like.
Suppose I want to send one word to the CPU, do I send 8 values encoded in a binary format or 1 value encoded in a 256-value scheme?
As in, does the signal ever only have two levels and the cpu knows that it must read 8 values to form a word? Or does every signal have 256 levels and one value is a word?
Computers today are either 8-bit, 16-bit, 32-bit, or 64-bit. (In the past, there were other bus widths, such as 12 bits for the PDP-12, and 36 bits for the UNIVAC 1100 series -- both of which I programmed on in the 1970's -- but we'll forgot those for now).
This number, be it 8, 16, 32, or 64 refers to the data bus width, and is also the width of most registers in the machine. Note this is not the same as the width of the address bus -- if it were, then an 8-bit microcontroller could only address 256 bytes of memory (and I also once had an 8-bit computer with an 8-bit address bus, the Kenbak-1).
In general, 8-bit computers have 16-bit address busses, and can address 65536 bytes of memory and/or peripherals directly. In general, 16, 32, and 64 bit computers have address busses the same width as the data bus.
So when data is moved around in the machine, be it between a register in the CPU and memory, or between two registers in the CPU, the transfers take place using the bus width (8, 16, 32, 64). So the larger the data bus size, the more bytes of memory can be written to or read from memory, making the computer faster.
The concept of the "byte" was coined in the 1950's to denote an 8-bit storage location, but it did not really become popular until IBM came out with its IBM 360 series in the 1960's.
A word is the size of the data bus already discussed, whatever the number of bits transferred at one time, namely 8, 16, 32 or 64 bits.
So the 8086/8088 microprocessors, which had a 16-bit data bus, initially had a word size of 16-bits. This got ingrained in the software, so even though the x86 processors have now advanced from 16 to 32 bits, and then from 32 to 64 bits, the definition of a WORD in Windows software is still 16 bits, a DWORD (double word) is 32-bits, and a QWORD (quad word) is 64 bits.
In all cases, the bits in a byte (eight of them) can only take two values, 1 or 0. So they can go from 0000 0000 binary (zero) to 1111 1111 binary (255 decimal). I have divided each byte into two groups of four bits; those are called nibbles.
A bit with a value of 1 is represented by a logic high in the machine; years ago that meant a voltage of 5v, but this has been reduced over the years, first to 3.3v, then 2.5v, and most recently 1.8v. Actually many computers now use a combination of voltages; for example 3.3v for external connections, and 1.8v internally. The voltage representing 0, or a logic low, is always 0v.
These signals are either on or off (either logic high or logic low). Bits are sent in parallel down each line of an 8 (or 16 or 32 or 64) bit data path. But right after one byte or word whatever is sent, then another one may be sent. So if one looks at this data bus using a logic analyzer (kinda like a scope, but many more channels and only shows 1's and 0's), it looks something like this:
There are eight channels here, one for each bit of an 8-bit byte. They are numbered 0 to 7 from the bottom up on the left side. Time goes from left to right on the bottom scale. In this particular picture, there is no specific time scale, rather the numbers on the bottom are the sample number (the logic analyzer takes a snapshot of the data on a periodic basis). Samples may be taken for example every microsecond, or every 100 microsecond, or every millisecond, whatever the engineer sets them up to be.
To convert the bits from binary to decimal, one has to add up the values for each bit position:
bit 7 - 128
bit 6 - 64
bit 5 - 32
bit 4 - 16
bit 3 - 8
bit 2 - 4
bit 1 - 2
bit 0 - 1
If all bits are 1's, you get 128+64+32+16+8+4+2+1 = 255.
Starting from the left on the logic analyzer picture, the value on the bus is (from the bottom up) 1 1 0 0 0 0 0 0, or 3 decimal. At sample 1143, the value is 1 0 0 0 0 1 1 1 or 225 decimal.
The values shown on the logic analyzer screen are depicted as logic levels, so the waveforms are perfect square waves -- either high or low. If one would look at the same signals with a scope and zoom in, there will be some variations at the beginning and ending of each transition from low to high and high to low (called ringing), but it would still look mostly like a square wave (and not a sine wave for example).
So to answer your original question, the waveform above is what the signal for each bit actually looks like to the CPU.
Because of the ringing and noise at the top and bottom of the waveform, the logic circuitry defines maximum values for a logic 0 and minimum vales for a logic 1. For example, if this was 5v TTL (transistor-transistor) logic, then anything below 0.8v is considered a logic 0, and anything above 2v is considered a logic 1. Anything in between these margins is undefined (and can be interpreted as either a 1 or 0, perhaps erroneously.
Eight values forming a word. There are really only two levels.
However, if you look on a scope, you'll notice that at high speed the edges of the theoretically "square" wave are quite rounded.
