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I've created a log2 AGC for an FPGA project, similar to Dan Boschen's solution in this question. I implemented a hardware version of log2 based on Dan's linked page in the previous question - efficient floating point log2 computation.

For the antilog2 operation, I used simple bit shifting for the integer component, but resorted to using Horner's rule and the set of coefficients from robert bristow-johnson. This works very well, but I require several multipliers for the fractional part of the exponent.

Is there an algorithm to approximate antilog2 of the fractional component of fixed-point numbers efficiently, in a similar manner to the Dan's efficient log2?

I realise I can use a simple lookup table to achieve a multiplier-free version, but I'm interested if there is already something out there using simple bit shifting and recasting tricks.

WannabeDSP
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    Interesting question! Not sure if it helps, but this repo has some table-based approaches that might mean not re-inventing the wheel. – Peter K. Feb 14 '24 at 14:11
  • Thanks for sharing this repo Peter. This will definitely help if I have to resort to tables. – WannabeDSP Feb 16 '24 at 06:05
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    I'm glad you were able to put it to use! – Dan Boschen Feb 16 '24 at 15:19
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    How approximate can it be, and how do you define "efficient"? Without knowing that there's no way of knowing what you might find best or sufficient. – TimWescott Feb 17 '24 at 16:44
  • Fair point @TimWescott. By efficiency, I mean that I'd like to trim FPGA resources in both DSP slices and LUTs. In terms of the estimation accuracy, I'd be happy with 1-2 dB. Granted I don't have an exact quantitative measure at the moment, but I'm just playing around with a few concepts to try target optimal resource usage on my FPGA. – WannabeDSP Feb 20 '24 at 08:19

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