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I am trying to understand if the new M2 Macs support Third Level Address Translation (TTBR0_EL3) which in the ARM world is called Stage 3 Translation in the ARM specification?

Gabriel Fair
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  • Just to confirm what you're asking about... SLAT is usually "second level address translation", which the M2 supports. Or are you asking about the existence of TTBR0_EL3? – jksoegaard Oct 19 '22 at 21:38
  • Yes you are right. Sorry I am new to this and are confusing the terms – Gabriel Fair Oct 22 '22 at 12:54

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Yes, the M2 Macs do have TTBR0_EL3 and support this type of address translation.

I assume you mean TLAT in the context of the secure monitor, and not in terms of nested layers of virtualisation.

jksoegaard
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  • Actually, I am not aware of the difference, could you elaborate on this? – Gabriel Fair Oct 28 '22 at 17:40
  • Hmm, can you explain the context of your question? - Why is it you want to ask the question? We might be talking about two entirely different things here. – jksoegaard Oct 29 '22 at 21:32
  • That has been asked @jksoegaard - https://apple.stackexchange.com/q/466761/5472 – bmike Dec 04 '23 at 01:22
  • @bmike Actually that question is about something entirely different - it is about nested virtualization. This question is about stage 3 memory address translation in EL3. Hardware assisted virtualisation software such as hypervisors run in EL2 - and they make use of what is known as stage 2 memory address translation. MAT is not the main component of hardware assisted virtualization. – jksoegaard Dec 04 '23 at 08:35